This invention relates to a chip-type solid electrolytic capacitor using a sintered body of a valve metal as an anode member and a method of producing the same and, in particular, to a chip-type solid electrolytic capacitor having a large capacity and a low equivalent series resistance (hereinafter abbreviated to ESR) and a method of producing the same.
In a solid electrolytic capacitor, an oxide layer obtained by electrolytic oxidation of an anode member is used as a dielectric member. The anode member comprises a sintered body of a so-called valve metal, such as aluminum, tantalum, niobium, titanium, hafnium, and zirconium, allowing formation of the oxide layer which is dense and highly insulative.
Typically, the solid electrolytic capacitor mentioned above is produced by a method comprising steps of forming an oxide layer by electrochemical anodic oxidation of a sintered body of a valve metal to serve as an anode member, forming a cathode layer and attaching a cathode terminal thereto, and attaching an anode terminal to an anode lead, thereby obtaining the capacitor For example, manganese dioxide is used as the cathode layer. In order to further improve the frequency characteristic, development is made of a solid electrolytic capacitor in which a conductive polymer is used as the cathode layer so as to reduce the ESR.
Referring to FIGS. 1A and 1B, a typical conventional chip-type solid electrolytic capacitor will be described. As shown in FIGS. 1A and 1B, the solid electrolytic capacitor comprises a capacitor element 1, an anode lead 2, a cathode terminal 3, and an anode terminal 6. The capacitor element 1 comprises an anode member 7, an oxide layer 8, and a cathode layer 9. The anode lead 2 is extracted from the anode member 7. The above-mentioned components are enclosed in an encapsulating resin 10 formed by resin molding.
As illustrated in FIG. 1A, the anode lead 2 is insulated from the cathode layer 9 by the oxide layer 8. As illustrated in FIG. 1B, the cathode terminal 3 and the anode terminal 6 are generally formed into shapes along the encapsulating resin 10 so as to be adapted to surface mounting.
The chip-type solid electrolytic capacitor having such a structure suitable for surface mounting is small in size, large in capacitance, and excellent in frequency characteristic and is widely used in a power supply circuit of a CPU and the like. However, as an operation frequency of the CPU becomes higher, there is an increasing demand for an improvement in noise characteristic of the power supply circuit as well as an increase in allowable ripple current. As a consequence, a capacitor further lowered in ESR is required.
Further, an apparatus to which the CPU is mounted is under development towards a smaller size and an advanced function. Accordingly, it is necessary to simultaneously satisfy not only the demand for a lower ESR but also the demand for a small size, a large capacitance, and a thin profile.
Generally, if a plurality of capacitors are connected in parallel, a total capacitance (Ctotal) and a total ESR (ESRtotal) are given by:Ctotal=C1+C2+ . . . +Cn  (1)1/ESRtotal=1/ESR1+1/ESR2+ . . . +1/ESRn  (2)Herein, Ci and ESRi represent the capacitance and the ESR of an i-th (i being a natural number between 1 and n) capacitor, respectively.
Therefore, by connecting a plurality of capacitor elements having the shape illustrated in FIG. 1A in parallel, the capacitance will be increased and the ESR will be reduced. This also applies to the case where the solid electrolytic capacitor is operated as a transmission-line noise filter.
Japanese Patent Application Publication No. 2001-284192 (Reference 1) discloses a first conventional technique of connecting a plurality of capacitor elements in parallel. Specifically, anode leads of a plurality of capacitor elements having the structure illustrated in FIG. 1A are connected to an anode terminal comprising a lead frame. A cathode layer of at least one capacitor element is connected to a cathode terminal comprising a lead frame.
Referring to FIG. 2, connection of a plurality of capacitor elements disclosed in Reference 1 will be described. In the figure, two capacitor elements 1d are connected to each other by the use of a silver paste through a cathode terminal 3c comprising a lead frame. Anode leads 2d are connected to opposite surfaces of an anode terminal 6 comprising a lead frame, respectively.
The present inventor developed a second conventional technique as a further improvement of the first conventional technique disclosed in Reference 1. The invention related to the second conventional technique is a subject of Japanese Patent Application No. 2003-106565 (not yet published). In the second conventional technique, a plurality of capacitor elements are connected in the following manner. A plate-like anode terminal is provided with at least one slit and divided by the slit into a plurality of parts, which are bent in a direction perpendicular to a plane of the anode terminal to form branched portions. Anode leads of the capacitor elements are individually connected to the branched portions of the anode terminal, respectively.
Referring to FIG. 3, connection of a plurality of capacitor elements disclosed in the second conventional technique will be described. In FIG. 3, two capacitor elements 1a and 1c are connected to each other. Anode leads 2a and 2c are extracted from the capacitor elements 1a and 1c, respectively. A cathode terminal 3d is interposed between the capacitor elements 1a and 1c. The anode leads 2a and 2c are connected to an anode terminal 6a. 
As illustrated in FIG. 3, the anode terminal 6a has a plate-like shape and has an end portion divided by a slit into two parts, which are bent in a vertical direction in FIG. 3 to form branched portions. Each of the anode leads 2a and 2c is extracted from a side surface of each of the capacitor elements 1a and 1c and is positioned in the vicinity of an end portion of the side surface. The capacitor elements 1a and 1c are laminated so that the anode leads 2a and 2c are apart from each other.
The capacitor elements 1a and 1c are connected through the cathode terminal 3d. Therefore, a cathode layer (not shown) formed on a surface of each capacitor element is connected to the cathode terminal 3d. In Reference 2, the anode leads 2a and 2c are connected to the anode terminal 6a in the above-mentioned manner so that an interference between nuggets formed by welding or between fillets formed by brazing is avoided and the variation in bonding strength is suppressed.
However, in the techniques disclosed in the above-mentioned references, the capacitor elements are almost individually and separately bonded to the cathode terminal. The surface conditions of the capacitor elements are nonuniform. Further, the amount of a conductive adhesive applied to bond the capacitor elements and the cathode terminal is not uniform. The two capacitor elements are individually connected to opposite surfaces of the cathode terminal by the conductive adhesive, respectively. Therefore, nonuniformity or variation tends to occur in bonding strength between the capacitor elements and the cathode terminal. For example, the bonding strength between one capacitor element and the cathode terminal may be within a managing standard while the bonding strength between the other capacitor element and the cathode terminal may not meet the standard. Consequently, the variation in bonding strength is difficult to suppress. This may result in variation in characteristic of a solid electrolytic capacitor as a finished product.